At VLSI 2026, the premier IEEE conference for microelectronics technology and circuits, one message stood out: in the AI era, scaling compute challenges span the entire stack—from systems to devices, memory, packaging, and manufacturing.
That’s why Applied Materials convened its inaugural VLSI panel to tackle a critical question: What limits compute—and what will it take to break those limits?
Before 300 attendees from industry and academia, Applied’s Kevin Moraes (VP of Strategy and Marketing) moderated a discussion between technology leaders from NVIDIA, Intel, Samsung Electronics, and Applied. The main takeaway: cross-stack challenges demand cross-stack solutions—and the collaboration to achieve them.
AI workloads reshape system requirements
NVIDIA’s Mahmut Ersin Sinangil (Distinguished Research Scientist) highlighted that AI is now defined by a broader mix of workloads with distinct requirements:
- Training demands massive throughput and compute scale
- Agentic AI introduces dynamic, heterogeneous workloads where token-to-token latency is critical
- Physical AI requires real-time response, increasing demands on latency and energy efficiency across cloud, data-center, and edge deployments.
Intel’s Chris Auth (VP & GM, Manufacturing Development and Customer Engineering) added that in these dynamic environments, the CPU is resurging as a central conductor—coordinating data movement and putting more emphasis on transistor performance and interconnect efficiency.
Data movement becomes new bottleneck
As AI shifts toward agentic and physical workloads, data movement becomes an increasingly critical limiter alongside compute. “Compute is extremely important, but we need to feed it with data,” said Mahmut Ersin (NVIDIA). “The system processes data and produces output, which it then feeds back into itself to do reasoning and provide better answers. You don’t want your GPUs running idle, so data movement becomes really important.”
This makes bandwidth a fundamental priority, per Samsung’s Jin‑Woo Han (VP, DRAM Technology Development). But scaling bandwidth introduces new tradeoffs:
- Higher bandwidth requires higher data rate with more I/O, increasing thermal load
- Rising heat forces reductions in power
- Lower power ultimately constrains bandwidth and system performance
The core challenge becomes: How can the industry increase compute bandwidth without proportionally increasing thermal and power loads?
Next-gen devices and interconnects drive scaling
Jin‑Woo (Samsung) outlined several paths forward. Physical scaling remains foundational, as smaller devices can deliver greater density and bandwidth at similar energy. But as Moore’s Law slows, the industry is shifting toward vertical memory architectures, including vertical cell designs in 4F2 and DRAM stacking.
He also highlighted a key shift in memory scaling: decoupling DRAM cell arrays and peripheral logic onto separate wafers, then bonding them—so each can be optimized independently with different thermal budgets, delivering higher‑performance transistors in both the periphery and the memory array.
Beyond device scaling, the panel highlighted interconnect materials innovation as critical to improving data movement between devices. As interconnects shrink, rising resistance and capacitance drive up energy costs. As Mahmut Ersin (NVIDIA) noted, “If data must move, it must move as efficiently as possible.”
Advanced packaging takes center stage in scaling
Jin‑Woo (Samsung) pointed to advanced packaging as a key enabler of direct logic‑memory integration to shorten data paths. The goal is to stack DRAM on logic with advanced bonding, allowing memory to function more like a processor cache.
While 3D packaging can unlock major system‑level gains, Applied’s Bala Haran (VP, Integrated Materials Solutions) cautioned it also escalates materials and integration complexity due to many more interfaces. Bala highlighted hybrid bonding as an example. It dramatically increases I/O density between chips, but achieving the necessary precision requires co-optimization across materials, process technology, and process control.
To enable next-generation architectures, Applied is developing integrated platforms like the Kinex™ hybrid bonding system. It combines clean, activation, bonding, and metrology in a single flow to deliver the required accuracy for a wide range of applications including 3D integrated circuits, HBM, co-packaged optics, and sensor integration.
Thermal limits drive materials innovation
As 3D integration increases, Chris (Intel) emphasized that thermals are becoming a defining constraint. This calls for heat dissipation through copper structures and a growing focus on materials innovation.
Bala (Applied) added that active cooling will require materials that are both thermally conductive and electrically insulating. However, adopting new materials is complex, given the stringent performance, integration, and manufacturability requirements. A key bottleneck is the industry’s sequential handoff model, which slows progress.
To accelerate the innovation and commercialization of new solutions, Bala emphasized the need for earlier, deeper ecosystem collaboration—highlighting initiatives like the global EPIC™ platform, which convenes partners across the value chain to tackle inflection points in parallel.
AI era demands deeper ecosystem collaboration
Ultimately, the scale of these challenges is too great for any company to solve alone. As system and architectural complexity grows, Chris (Intel) stressed the need for structured, multi‑party collaboration across logic, memory, systems, and materials and equipment suppliers.
The next phase of compute scaling will depend on coordinated advances across the entire stack. Building better compute systems starts with building better systems for collaboration. Only then can the industry keep up with the demands of the AI era.
