Synopsys Expands Hardware-Assisted Verification Portfolio with AMD-Powered HAPS-200 and ZeBu-200 Systems for Next-Gen Semiconductor Design
Synopsys, Inc. (Nasdaq: SNPS) has announced a major expansion of its industry-leading hardware-assisted verification (HAV) portfolio with the launch of the next-generation HAPS-200 prototyping and ZeBu-200 emulation systems, powered by the latest AMD Versal™ Premium VP1902 adaptive SoC. These cutting-edge systems deliver unparalleled runtime performance, faster compile times, and enhanced debug productivity, addressing the escalating complexity of modern SoC and multi-die designs. Built on Synopsys’ new Emulation and Prototyping (EP-Ready) Hardware platform, these solutions optimize customer return on investment (ROI) by enabling seamless reconfiguration for both emulation and prototyping use cases.
Addressing Unprecedented Verification Challenges
As semiconductor designs approach hundreds of billions of gates per chip and millions of lines of software code, advanced verification poses unprecedented challenges. “With the industry approaching 100s of billions of gates per chip and 100s of millions of lines of software code in SoC and multi-die solutions, verification of advanced designs poses never-before-seen challenges,” said Ravi Subramanian, Chief Product Management Officer at Synopsys. “Continuing our strong partnership with AMD, our new systems deliver the highest HAV performance while offering ultimate flexibility between prototyping and emulation use cases. Industry leaders are adopting Synopsys EP-Ready Hardware platforms for silicon-to-system verification and validation.”
The new ZeBu Server 5 system further enhances scalability, supporting designs beyond 60 billion gates (BG) to address the growing demands of multi-die architectures and complex software integration. It continues to offer industry-best density, optimizing data center space utilization—a critical factor for companies managing large-scale verification workflows.
HAPS-200 and ZeBu-200: Setting New Standards in Performance
The HAPS-200 prototyping system delivers an impressive 2X performance increase over its predecessor, the HAPS-100, along with 4X improved debug performance. Leveraging the existing HAPS-100 ecosystem, the HAPS-200 supports mixed HAPS-200/100 configurations, scalable from single FPGA setups to multi-rack installations with capacities of up to 10.8 billion gates (BG). This flexibility makes it ideal for a wide range of applications, from early software development to full-system validation.
Similarly, the ZeBu-200 emulation system extends design capacity to 15.4 BG while offering up to 2X higher runtime performance compared to the previous generation ZeBu EP2. With faster compile times, reduced turnaround time, and enhanced development productivity, the ZeBu-200 is a game-changer for engineering teams working on large-scale designs. It also features 8X better debug bandwidth, providing 200 GB of debug trace memory per module and improved job scheduling and relocation capabilities.
Industry Validation: NVIDIA and Beyond
The impact of Synopsys’ new systems is already being felt across the semiconductor industry. Narendra Konda, Vice President of Hardware Engineering at NVIDIA, highlighted the critical role of the HAPS-200 in accelerating software development: “With the increasing market requirements for handling large AI computational datasets driving the need for enormous GPU and CPU computational power, the development time for NVIDIA’s next-generation AI systems has become highly compressed to a yearly release cycle, necessitating best-in-class prototyping solutions. Synopsys HAPS-200 offers the fastest prototyping speed in the industry. The 50 MHz performance we’ve achieved with HAPS-200 has been key to boosting productivity for our software development teams. We look forward to scaling our HAPS-200 deployment to take full advantage of its capabilities.”
EP-Ready Hardware: Maximizing ROI
The HAPS-200 and ZeBu-200 systems are built on the Synopsys EP-Ready Hardware platform, which eliminates the need for customers to decide upfront on the balance between emulation and prototyping hardware. This flexibility ensures maximum ROI by allowing users to dynamically adapt their workflows as project requirements evolve. The platform supports direct and scalable connectivity through cables and hubs, while leveraging Synopsys’ broad portfolio of transactors and speed adaptors for leading interface protocols.
Salil Raje, Senior Vice President and General Manager of AMD’s Adaptive and Embedded Computing Group, emphasized the transformative potential of this collaboration: “The future of emulation and prototyping demands unprecedented performance, adaptability, and scalability. By integrating the AMD Versal Premium VP1902 adaptive SoC into Synopsys’ EP-Ready platforms, we’re not only improving performance metrics but also transforming how engineering teams validate and optimize their most ambitious ASIC and SoC designs. Our longstanding partnership with Synopsys empowers design teams to tackle their most complex verification challenges, from AI/ML workloads to multi-die architectures, while dramatically accelerating time to market.”
Supporting Arm Ecosystem and Multi-Die Designs
Synopsys’ new systems also play a pivotal role in advancing the Arm Total Design ecosystem. Kevork Kechichian, Executive Vice President of Solutions Engineering at Arm, noted the significance of Synopsys’ contributions: “Synopsys is a key member of Arm Total Design, bringing critical tools and advanced HAV capabilities to quickly and reliably validate solutions built on Arm Compute Subsystems (CSS). The new ZeBu-200 and HAPS-200 hardware platforms will assist our mutual customers in integrating Arm CSS into their designs with improved turnaround times to meet the demanding requirements for complex data center infrastructure and automotive systems.”
Synopsys’ “Modular HAV” methodology, already in use with HAPS prototyping, has been extended to ZeBu Server 5. This approach leverages Synopsys’ broad portfolio of complete, silicon-proven interface IP to significantly reduce compile time and compute resources, enabling emulation for the largest multi-die designs.
Accelerating Software Bring-Up with Hybrid Technology
Synopsys’ hybrid technology combines virtual models running on a host server with HAV systems, enabling accelerated software bring-up processes. The Synopsys Virtualizer™ now supports multi-threading technology, allowing users to achieve a full Android boot in less than 10 minutes. This advancement is particularly valuable for companies developing complex systems requiring rapid software integration.
Why This Matters for the Semiconductor Industry
The launch of the HAPS-200 and ZeBu-200 systems underscores Synopsys’ commitment to addressing the growing demands of advanced semiconductor design. By delivering industry-leading performance, scalability, and flexibility, these systems empower engineering teams to tackle the most complex verification challenges while significantly reducing time to market. As the semiconductor industry continues to push the boundaries of innovation, Synopsys’ expanded HAV portfolio positions it as a key enabler of next-generation technologies.
For more information about Synopsys’ latest advancements in hardware-assisted verification, visit Synopsys’ official website.
