Expanded partnership delivers certified design flows, silicon-proven IP, and AI-driven EDA to accelerate advanced-node chip development and time-to-market
Cadence Design Systems, listed on Nasdaq: CDNS, has announced a significant expansion of its long-standing collaboration with TSMC, the world’s leading semiconductor foundry. This strengthened partnership is designed to accelerate the development of next-generation artificial intelligence (AI) silicon by delivering a comprehensive, signoff-ready design ecosystem tailored for advanced semiconductor nodes.
As AI workloads continue to scale in complexity and performance demands, the semiconductor industry is under increasing pressure to deliver more powerful, energy-efficient chips within compressed development timelines. The enhanced Cadence–TSMC collaboration directly addresses these challenges by combining cutting-edge electronic design automation (EDA) tools, silicon-proven intellectual property (IP), and certified design flows optimized for TSMC’s most advanced process technologies, including N3 (3nm), N2 (2nm), A16™, and the upcoming A14 node.
At a strategic level, the collaboration is focused on enabling Design Technology Co-Optimization (DTCO), a methodology that tightly integrates chip design with manufacturing process capabilities. By aligning design tools, IP, and process technologies more closely, the partnership helps semiconductor companies reduce design iterations, improve correlation between simulation and silicon results, and ultimately accelerate time-to-market with higher confidence in first-pass success.
A key outcome of this expanded effort is the delivery of a fully integrated, end-to-end design infrastructure that supports the entire semiconductor development lifecycle. This includes front-end design, synthesis, implementation, verification, signoff, and advanced packaging. The infrastructure is “signoff-ready,” meaning it is validated to meet stringent manufacturing requirements, ensuring that designs can proceed to fabrication with minimal risk.
According to Chin-Chi Teng, innovation in AI silicon at advanced nodes requires a holistic approach that spans the entire design cycle—from system-on-chip (SoC) architectures to chiplet-based and 3D integrated circuit (3D-IC) designs. He emphasized that the collaboration with TSMC advances Cadence’s dual strategy of “Design for AI” and “AI for Design,” integrating certified flows with proven IP while building a foundation for agent-driven, AI-assisted engineering workflows.
From TSMC’s perspective, the partnership plays a critical role in supporting customers facing rapidly evolving compute requirements. Aveek Sarkar highlighted that the convergence of AI-driven workloads and shorter design cycles necessitates not only advanced process technologies but also streamlined design methodologies and validated IP. Through its Open Innovation Platform® (OIP), TSMC collaborates with ecosystem partners like Cadence to ensure customers can confidently design cutting-edge chips using the latest manufacturing and packaging innovations, including its 3DFabric® technologies.
One of the foundational pillars of the collaboration is Cadence’s extensive portfolio of silicon-proven IP optimized for TSMC’s advanced nodes. This includes high-performance interfaces and memory solutions such as DDR5 12.8G MRDIMM, PCIe® 6.0, LPDDR6/5X running at 14.4G, and next-generation HBM4E memory operating at 16G speeds. Additionally, the Cadence® Artisan® foundation IP portfolio is already being deployed in production designs on TSMC’s 3nm process, demonstrating real-world validation and industry adoption.
Complementing this IP portfolio is a suite of certified, end-to-end EDA tools that support the full spectrum of chip design requirements. These tools include advanced digital implementation systems, custom and analog design environments, simulation platforms, thermal analysis solutions, power integrity tools, and physical verification systems. All of these technologies are certified for TSMC’s N2 and A16 nodes, with ongoing collaboration to support the A14 process design kits (PDKs). This level of certification ensures that design teams can achieve tapeout-quality results more efficiently, particularly for demanding AI and high-performance computing (HPC) applications.
The collaboration also extends into the rapidly evolving domain of 3D-IC and heterogeneous integration. Cadence’s Integrity™ 3D-IC Platform supports TSMC’s reference flows for stacked-die architectures, enabling designers to build complex, multi-die systems with improved performance and efficiency. Enhancements in Virtuoso® Studio further enable heterogeneous integration, including support for silicon photonics, which is increasingly important for high-speed data transfer in AI systems. Additional capabilities, such as thermal-aware design flows and signal integrity analysis, ensure that these advanced systems can operate reliably under real-world conditions.
A major innovation area within the partnership is the integration of agentic AI into the chip design process—referred to as “AI for Design.” Cadence is developing “agent-ready” infrastructure that transforms traditional tool-based workflows into goal-driven, AI-assisted processes. These systems leverage machine learning and domain-specific reasoning to automate complex design tasks, optimize performance, power, and area (PPA) trade-offs, and accelerate convergence across the design space.
This shift toward AI-driven design is particularly important as chip complexity continues to grow exponentially. By embedding AI into synthesis, implementation, and optimization tools, Cadence enables engineers to achieve higher productivity and better outcomes with fewer manual interventions. These capabilities are further enhanced through alignment with TSMC’s NanoFlex™ Pro standard cell architecture, which supports fine-grained optimization of speed and power efficiency during key design stages such as floorplanning and placement.
The collaboration also incorporates advanced innovations such as TSMC’s A16 Super Power Rail technology, which routes power delivery networks on the backside of the chip. This approach enables higher transistor density and improved performance, addressing one of the key bottlenecks in advanced node design.
In the custom design domain, Cadence has embedded agentic AI capabilities into its Virtuoso Studio environment, enabling automated circuit optimization tailored to TSMC’s process technologies. This includes support for analog design migration across nodes, allowing designers to transition efficiently from N2 to future nodes like A14 without compromising performance or reliability.
The impact of the Cadence–TSMC collaboration is already evident in strong customer momentum. Semiconductor companies across the AI and HPC ecosystem are actively designing chips on TSMC’s 3nm and 2nm nodes, leveraging the combined capabilities of certified flows, validated IP, and advanced design infrastructure. This widespread adoption underscores the critical role of ecosystem partnerships in enabling next-generation innovation.
Industry leaders have also highlighted the importance of such collaborations. NVIDIA, through Tim Costa, emphasized the need for a fundamentally new approach to chip design that integrates accelerated computing and AI at every stage. Similarly, Arm, represented by Eddie Ramirez, noted that ecosystem collaboration is essential for delivering efficient compute platforms at advanced nodes.
Emerging companies are also benefiting from this ecosystem. Positron, for example, is leveraging Cadence’s PCIe 6.0 SerDes IP on TSMC’s N3P process to develop specialized AI inference accelerators optimized for transformer workloads. According to Thomas Sohmers, the Cadence–TSMC partnership provides a reliable and predictable path to tapeout, enabling rapid innovation and faster time-to-market.
In summary, the expanded collaboration between Cadence and TSMC represents a comprehensive effort to redefine how next-generation AI silicon is designed and delivered. By integrating advanced process technologies, silicon-proven IP, certified design flows, and AI-driven methodologies, the partnership equips semiconductor companies with the tools and infrastructure needed to navigate increasing complexity and deliver breakthrough innovations. As AI continues to drive demand for more powerful and efficient chips, collaborations like this will play a pivotal role in shaping the future of the semiconductor industry.
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