Unlocking Heterogeneous Compute Architectures: Baya Systems, Imagination Tech, and Andes Technology to Present at RISC-V CON Silicon Valley
In a groundbreaking collaboration, Baya Systems, Imagination Technologies, and Andes Technology are set to present a joint technical session at Andes RISC-V CON Silicon Valley, focusing on innovative strategies for optimizing heterogeneous system-on-chip (SoC) architectures. This session will explore the intricate dynamics of memory hierarchy, CPU-GPU interaction, and real-world integration techniques essential for accelerating AI, machine learning, and graphics-intensive workloads in edge environments.
The session, titled “Unleashing the Power of Heterogeneous Computing,” will be led by Dr. Eric Norige, Chief Software Architect at Baya Systems, and Pallavi Sharma, Director of Product Management at Imagination Technologies. Together, they will delve into how real-time interaction between CPU and GPU subsystems impacts memory hierarchy, bandwidth allocation, and latency. Attendees will gain actionable insights into architecture-level decisions that influence frame rendering, AI inference efficiency, compute distribution, and software platforms that provide continuous design support from concept to deployment.
Addressing the Complexity of Modern Workloads
As AI, machine learning, and graphics workloads grow increasingly complex, SoC designers face mounting pressure to optimize performance while maintaining energy efficiency. “The complexity of modern workloads demands architectural agility,” said Dr. Eric Norige. “By analyzing subsystem interaction and designing intelligent cache and memory hierarchies, we can maximize performance gains across AI and graphics domains—without overengineering the silicon.”
This collaborative effort leverages the strengths of each company to address these challenges. Baya Systems brings its expertise in software-defined IP and architecture tooling, enabling workload simulation, cache modeling, and interconnect optimization. Imagination Technologies contributes high-performance, low-power GPU IP tailored for edge inference and advanced graphics. Meanwhile, Andes Technology provides a comprehensive RISC-V IP portfolio, including out-of-order cores and performance modeling tools for system-level validation.
Key Highlights of the Technical Session
- Cache and Memory Hierarchy Analysis
Using Baya’s CacheStudio™ software, Norige and Sharma will demonstrate how developers can simulate cache architectures, evaluate memory access patterns, and optimize coherence between CPU and GPU cores. This analysis ensures efficient memory usage, reducing latency and power consumption while improving throughput. - Platform-Agnostic Integration
The session will showcase how CacheStudio supports seamless integration of Imagination GPU IP and Andes RISC-V cores within a unified, modular environment. This approach accelerates development timelines and enhances silicon area efficiency, empowering designers to create scalable RISC-V platforms. - AI and Graphics Use Cases
Live demonstrations will model real-world inference workloads and graphics pipelines, highlighting how compute offload, memory arbitration, and shared cache tuning can optimize performance. These examples illustrate how strategic design decisions can reduce latency, lower power usage, and increase overall system throughput.
Technologies Driving Innovation
The session will feature cutting-edge technologies from all three companies:
- Baya Systems: Offers software-defined IP and architecture tooling for SoC and chiplet design, including workload simulation, cache and memory hierarchy modeling, and interconnect optimization. These tools enable developers to make informed design decisions early in the process.
- Imagination Technologies: Provides high-performance, low-power GPU IP designed for edge inference, industrial AI, and advanced graphics applications. Their solutions are optimized for demanding workloads while maintaining energy efficiency.
- Andes Technology: Delivers a complete RISC-V IP portfolio, including out-of-order cores and performance modeling tools for system-level validation. Their offerings support workload-driven SoC design and optimization, aligning with the growing adoption of RISC-V architectures.
Why This Matters for Developers and Designers
For developers and SoC architects, understanding the nuances of heterogeneous computing is critical to meeting the demands of modern AI and edge workloads. Traditional design approaches often struggle with inefficiencies in memory hierarchy, bandwidth allocation, and latency, leading to suboptimal performance and higher power consumption.
The insights shared during this session will empower attendees to:
- Optimize Performance: Learn how to balance CPU and GPU interactions to achieve maximum throughput and efficiency.
- Reduce Power Consumption: Discover techniques for minimizing energy usage without compromising performance.
- Accelerate Development: Leverage platform-agnostic tools and modular environments to streamline the design process.
- Future-Proof Designs: Gain a deeper understanding of scalable architectures that adapt to evolving workload requirements.
A Collaborative Vision for the Future
The collaboration between Baya Systems, Imagination Technologies, and Andes Technology underscores a shared commitment to advancing SoC design through innovation. “Imagination is thrilled to collaborate with Baya Systems and Andes Technology to explore innovative SoC strategies,” said Pallavi Sharma. “By combining our GPU expertise with system-level insights, we aim to empower developers to create efficient, scalable RISC-V platforms that meet the demands of modern AI and graphics workloads.”
“As RISC-V adoption grows, so does the demand for smarter, workload-driven SoC design and optimization,” added Marc Evans, Director of Business Development and Marketing at Andes Technology. “This session is a great opportunity for developers to explore integration strategies that deliver real performance gains.”
